The present invention relates to a timing control circuit for changing a delay of a signal employed in an electronic circuit to thereby carry out timing control, and to a semiconductor device having such a timing control circuit. The present invention also relates to a technique effective for application to a clock synchronous memory such as a synchronous DRAM (Dynamic Random Access Memory), a synchronous SDRAM (Static Random Access Memory).
A clock access time (corresponding to the time required for an LSI to output a data signal in response to a clock signal) of a clock synchronous LSI (Large-Scale Integrated circuit) is rate-controlled by, for example, an operation delay developed in an input clock buffer, a wiring delay of a clock signal from the clock buffer to an output data buffer, and an output operation delay of a data signal outputted from the output data buffer, etc. For example, a delay time corresponding to the sum td (=td1+td2+td3) of a delay time td1 developed in the input clock buffer, a delay time td2 developed in wire or interconnection, and a delay time td3 developed in the output data buffer (corresponding to a data register and an output buffer) is produced until a clock signal for defining output timing of the output data buffer is inputted to an external clock terminal and data is outputted from the output data buffer.
The delay time td1 developed in the input clock buffer, the delay time td2 developed in the long wire and the delay time td3 developed in the data register and output buffer respectively varied due to a variation in process and changes in source voltage and temperature. Thus, the sum td of the delay times greatly varied.
Therefore, when a clock to be used is made fast and a cycle time is shortened, a time domain in which, for example, data outputted to the outside of LSI from the output data buffer can be received at the data receiving site where the data is received, becomes narrow, thus making it difficult to design a system.
It is thus considered that a timing control circuit is applied to solve the above problem. This aims to arrange the phase of a clock signal propagated through LSI by means of the timing control circuit in order to synchronize the clock signal received by LSI with timing provided to output data.
When the timing control circuit is placed immediately after an input clock buffer, for example, a clock signal produced by the input clock buffer is delayed td1 with respect to a clock signal at an external clock terminal. The timing control circuit produces a delay of m×tck−(td1+td2+td3). Here, tck indicates a clock cycle time, m is an integer greater than 1 and is determined so as to meet or satisfy m×tck−(td1+td2+td3)>0. In doing so, a clock signal produced from the timing control circuit is delayed m×tck−(td2+td3) with respect to the clock signal inputted to the external clock terminal. As a result, an output data signal at an output data terminal is delayed m×tck, i.e., m clock cycles with respect to the clock signal inputted to the external clock terminal. However, this is equivalent to the fact that the output data signal is in synchronism with the clock signal inputted to the external clock terminal. Thus, the output data signal can be synchronized with the external clock signal received by LSI through the use of the timing control circuit. Even if changes in process, source voltage and temperature occur, and the delay time td1 developed in the input clock buffer, the delay time td2 developed in the long wire and the delay time td3 developed in the data register and output buffer change, the timing control circuit develops the delay of m×tck−(td1+td2+td3) with given accuracy and synchronizes the timing provided to perform data output with the clock signal. Therefore, a variation in timing for the data output can be reduced within the above accuracy.
A DLL (Delay-Locked Loop) circuit is known as the timing control circuit. The DLL circuit is comprised principally of a variable delay circuit, a phase comparator, a delay control circuit, and a dummy delay circuit for reproducing a delay tdrep developed in a specific circuit in a chip. The function of the DLL circuit is to output an internal clock signal which is delayed m×tck−tdrep with respect to an external clock signal. Here, m is an integer greater than 1 and is determined so as to meet m×tck−tdrep>0.
IEEE Journal of Solid-state Circuits, Vol. 33, No. 11, C. H. Kim et al. issued by Institute of Electrical & Electronic Engineers of US (IEEE), November in 1998, entitled “A 64-Mbit, 640-Mbyte/s Bidirectional Data Strobed, Double-Data-Rate SDRAM with a 40-mw DLL for a 256-Mbyte Memory System” (pp.1703-1709) is known as a first reference in which the DLL circuit has been described. The DLL circuit described in the reference comprises a variable delay circuit, a pad routing delay for receiving a clock signal outputted from the variable delay circuit, a phase comparator for comparing the phase of an output produced from the pad routing delay and that of a clock signal inputted to the variable delay circuit, and a delay control circuit for performing delay control of the variable delay circuit based on the result of phase comparison by the phase comparator. The interior of the variable delay circuit takes a multistage configuration of differential type buffers and inverters. Loads each comprised of voltage-controlled capacitance are provided at their corresponding outputs of respective differential stages. The voltage-controlled capacitance is controlled to change a delay of a signal, i.e., its phase. In the DLL circuit, the clock signal is set to the variable delay circuit and outputted as an internal clock signal after the elapse of a predetermined delay time. At this time, the delay time developed in the variable delay circuit is controlled by the delay control circuit. This control is performed in the following manner. First of all, the input clock signal is transmitted even to the phase comparator together with the variable delay circuit. After the clock signal has passed through the variable delay circuit, it passes through the pad routing delay and enters the phase comparator. The phase comparator compares the phase of the post-one cycle clock signal and that of the clock signal, which has passed through the variable delay circuit and pad routing delay. When the phase of the clock signal having passed through the variable delay circuit and pad routing delay lags that of the post-one cycle clock signal, the delay control circuit having received the result of comparison shortens the delay time developed in the variable delay circuit by one delay step or increment. When the phase of the clock signal leads that of the post-one cycle clock signal in reverse, the delay control circuit lengthens the delay time developed in the variable delay circuit by one delay step, thereby controlling the delay time of the variable delay time. Owing to the execution of the above control for a sufficient time interval, the timing for the clock signal having passed through the variable delay circuit and the pad routing delay can be matched with that for the clock signal, whereby an internal clock signal delayed m×tck−tdrep (where m=1) with respect to the input clock signal can be obtained.
A basic configuration similar to the above, which is related to the DLL circuit, has been described even in Japanese Patent Application Laid-Open No. Hei 8-147967.
1997 IEEE International Solid-State Circuits Conference Digest of Technical Papers, Atsushi Hatakeyama et al. issued by Institute of Electrical & Electronic Engineers of US (IEEE), February in 1997, entitled “A 256 Mb SDRAM Using a Register-Controlled Digital DLL” (pp.72-73) is known as a second reference in which DLL has been described. A timing control technique described in the second reference aims to divide the frequency of an externally input clock signal by a frequency-dividing circuit and supply the divided clock signal to a DLL circuit, and provide a second variable delay circuit identical to a variable delay circuit lying within the DLL circuit, supply the pre-division clock signal to the second variable delay circuit and delay-control the second variable delay circuit by a delay control circuit in a manner similar to the variable delay circuit lying within the DLL circuit, thereby to obtain an internal clock signal delayed m×tck−tdrep with respect to the input clock signal. Since the operating speed of the DLL circuit is made slow by the frequency-dividing circuit, the present technique is low in power consumption as compared with the technique described in the first reference as to this point. A description related to the invention in which the operating speed of a DLL circuit is rendered slow by a frequency-dividing circuit in the same manner as described above, has been disclosed even in Japanese Patent Application Laid-Open No. Hei 10-269773 (corresponding to U.S. Pat. No. 5,955,904).
A description related to the invention in which the number of variable delay circuits remains unchanged, and only the input of a phase comparator is divided by a frequency-dividing circuit to thereby make slow a phase comparison operating speed, has been disclosed in each of Japanese Patent Application Laid-Open Nos. Hei 10-209857 and 11-17529. Further, such a DLL circuit that a phase comparing operation is stopped after its lock-in, has been described in Japanese Patent Application Laid-Open No. Hei 11-17530. Japanese Patent Application Laid-Open No. Hei 11-15555 is known as another reference in which a DLL circuit has been described.
Further, a semiconductor integrated circuit provided with a circuit considered to be a DLL circuit in Japanese Patent Application Laid-Open No. Hei 6-350440 (corresponding to U.S. Pat. No. 5,572,557) has a variable delay circuit controlled based on the result of comparison by a phase comparator. Frequency-dividing circuits are provided at the input and output of the variable delay circuit. An output produced from the frequency-dividing circuit connected to the output of the variable delay circuit is outputted outside the semiconductor integrated circuit. This output signal passes through a fixed delay buffer and each mounted wire provided over a clock distribution buffer mounted or implemented on a printed circuit board together with the semiconductor integrated circuit so as to be fed back to one input of the phase comparator. The output of the frequency-dividing circuit on the input side of the variable delay circuit is coupled to the other input of the phase comparator. A clock signal is supplied to the variable delay circuit from the clock distribution buffer. In the technique described therein, however, each wire on the printed circuit board, which is placed outside a semiconductor chip, is interposed in a feedback path extending from the variable delay circuit to a fixed delay circuit of the clock distribution buffer. Therefore, when the frequency of a signal is high, the transmission of the signal cannot be performed correctly. Thus, the frequency-dividing circuits are considered to be provided in order to allow phase lock control by a reduction in the frequency of the signal on such a path. Japanese Patent Application Laid-Open No. Hei 6-350440 suggests even a configuration equivalent to a DLL circuit provided with a frequency-dividing circuit only on the output side of a variable delay circuit. In the present configuration, the frequency-dividing circuit is provided only within a range required to lower the frequency of a signal over a mounted board. An inventive idea that frequency-dividing circuits are provided to achieve low power consumption and they are placed at both the input and output of a variable delay circuit to provide one variable delay circuit, is nil.
Further, an idea that all the elements of structure employed in a clock reproducing circuit are formed over one semiconductor chip, has not yet been disclosed.